1. Field of the Invention
The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a structure of a device and a transistor which endures a high tolerance voltage and which allows a large amount of current to flow and a method for manufacturing the device or the transistor.
2. Description of the Related Art
As a device which has a high tolerance voltage such as silicon devices, there are known a VMOS (V-grooved Metal Oxide Semiconductor) transistor and a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor which are referred to as a vertical structure type transistor, and a RESURF (Reduced Surface Field) structure transistor or an L-DMOS (Lateral Double-Diffused Metal Oxide Semiconductor) transistor which are referred to as a horizontal structure type transistor. These devices and transistors are described in the xe2x80x9cModeling of the On-Resistance of LDMOS, VDMOS and VMOS Power Transistorsxe2x80x9d (IEEE Trans. on Electron Devices, Vol. ED-27, p356), a document published by S. C. Sun and J. D. Plummer in 1980. These transistors are characterized in that they have a high concentration p-type layer under the gate and a region named a drift layer provided between the gate and the drain in addition to the normal transistor structure. On the drift layer, a channel comprising an n-type conductive, and a metal electrode fixed to the source potential in parallel with the channel are provided on the surface of the substrate via an oxide film, or a p-type layer is provided in the substrate.
A breakdown of the power-FET which is caused by a voltage exceeding a tolerance voltage is finally determined by the fact that an electron current further increases by a positive return such that an increase in the electron current, the generation of holes (positive holes) by avalanche breakdown, the excitation of electrons by the positive carrier (holes) allows a destructive current to flow. The p-type layer immediately under the gate works in the same way as the channel dope layer used for the suppression of the short channel effect with a fine MOSFET. As a consequence, the leak current decreases in the OFF state of the transistor, and the avalanche breakdown caused by the seed of this leak current is not generated so that the generation of the holes is suppressed. The effect of the p-type layer which decreases the seed current of the avalanche breakdown contributes conspicuously toward an improvement in the tolerance voltage.
Since no depletion layer spreads in the n-type layer at a low drain voltage in the drift layer, the channel of the n-type layer has a low resistance. On the other hand, a large bias is applied between the n-type layer, and the p-type layer or a metal electrode at a high drain voltage with the result that the n-type layer is depleted. As a consequence, the n-type layer can serve as a high resistor. When the n-type channel is completely depleted, a uniform electric field is applied in the direction of the channel so that no concentration of the electric field is generated. Consequently, the avalanche breakdown is hardly generated and a high-tolerance voltage is provided. When the drift layer is set to a five-pole tube mode, the same effect as the cuss code connection at the so-called two FET with the result that a high frequency characteristic is not damaged.
However, in a compound semiconductor power-FET, no such drift layer is provided. This is because the compound semiconductor has a high surface state level unlike silicon with the result that this surface state level serves as the same function as the p-type layer, and it was not required to actively introduce the p-type layer. However, since the surface state level which serves in the same way as the p-type layer is formed with the implantation of the negative carrier from the gate electrode, the length of the surface state level is definite. The length of the surface state level does not stand in proportion to the distance between the gate and the drain like the drift layer described above, and the tolerance voltage is limited to about 20V.
Thus, in order to enhance the tolerance voltage, an attempt has been made to introduce the p-type layer in the same manner as the silicon device for the suppression of the short channel effect and for an effective operation of the drift layer. In the case where a transistor is formed on the semi-insulation substrate, the p-type layer is surrounded with the semi-insulation substrate and the non-doped layer with the result that the p-type layer is electrically drifted. However, in the case where the generation of the holes at the avalanche breakdown is small in amount, the potential of the p-type layer leads to the formation of p-n junction with the n-type layer of the source and the drain. Thus, the source side with a low voltage constitutes a normal direction junction so that the potential of the p-type layer becomes approximately equal to the source potential. In such a case, with the same mechanism with the case of the MOSFET, the tolerance voltage has improved in the OFF state in which the drain current does not flow.
However, when the drain voltage is allowed to be increased in the ON state, a permanent breakdown which invites the thermal breakdown is generated at a relatively low voltage. The cause of the permanent breakdown can be described as follows. In other words, at a high voltage more than a certain degree accompanied by the flow of the drain current, the holes begin to be generated resulting from the avalanche breakdown. When the holes are accumulated in the vicinity of the channel, the positive voltage is generated which invites an increase in the drain current. As a consequence, the positive return of a current increase which has been described before is generated which leads to the permanent breakdown. When the current begins to flow through the FET, the electric field is concentrated on the drain end in a channel having a uniform doping with the result that the generation of a high electric field can not be avoided in the ON state. As a consequence, virtually no effect on the tolerance voltage is generated with the introduction of the p-type layer buffer which is drifting. Consequently, a high-tolerance voltage operation on the order of several hundred Volts which is obtained in the silicon MOSFET cannot be obtained.
Furthermore, actually, in the power-FET, B class or AB class operation amplifiers are used in many cases in order to realize a higher efficiency. In the case of such operation mode, the gate voltage in the half period of the input AC signal, the gate voltage will be lowered to a level lower than the level of the voltage at which the channel is temporarily cut off. When the gate voltage is lowered to a negative voltage, the n-type channel which constitutes a barrier of the holes is depleted and the p-type layer hole flows into the gate over the channel portion. On the other hand, an opposite bias is applied in the half period, but the holes are not implanted into the channel because the gate is a shot key electrode, and only the electrons of the channel flow into the gate. As a consequence, the flow of the holes as a whole is directed only in one direction with the result that the p-type layer holes is pulled out in a one-sided manner. In the case where the p-type layer is electrically drifted from the other electrode, the potential of the p-type layer is lowered. The drift current is lowered in the same manner as at the time when a negative substrate bias is applied with the result that a large electric power cannot be generated.
Furthermore, in the drifting p-type layer, a similar decrease in the drain current is generated in another mechanism. In the power-FET, the drain voltage is largely changed. As a consequence, the potential of the drifting p-type layer is oscillated with the capacity junction with the drain and the channel. In a normal state, as has been described above, the potential of the p-type layer is approximate to the source potential. However, when the central voltage changes centering on this potential, a voltage in the normal direction of the p-n junction and a voltage in the opposite direction thereof are applied between the n-type layer and the p-type layer of the source in an alternate manner. At the time of the bias in the normal direction, the p-type layer holes flow into the source. Otherwise, electrons flow into the p-type layer from the source with the result that the p-type layer is charged with negative electricity.
On the other hand, at the time when the opposite bias is applied, both the electrons and the holes do not move. As a consequence, the potential of the p-type layer is shifted in an increasing manner to the negative potential to be stabilized. The change is very slow as compared with a high frequency that is handled as a signal because such change occurs at the leak current of the p-n junction. As a consequence, it seems that a negative bias is applied to the substrate in terms of DC for the high frequency signal with the result that the drain current decreases and a large output cannot be obtained.
In this manner, the OFF tolerance voltage of the drifting p-type layer can be raised, but the drifting p-type layer has problems such as the generation of a positive bias resulting from the avalanche and the generation of the negative bias resulting from the charged pumping. These problems can be solved and prevented by fixing the potential of the p-type layer from the outside in the same manner as the MOSFET. For the solution of these problems, it is required to form a contact to the p-type layer from the surface or to use the p-type substrate. The increase in the steps and the deterioration in the high frequency characteristic cannot be avoided, but no measures can be taken about such problems.
However, in the case where the potential of the p-type layer is fixed, the holes of the p-type layer begin to flow out to the gate when an excessively large negative bias is applied to the gate in the B class operation with the result that a gate leak is generated. The gate leak leads to the generation of noises by the gate current, the change in the gate bias and in the substrate bias, an increase in the consumed power and the like. Only with respect to the suppression of the flow of the holes, there is provided a method using a large hetero-barrier having a band gap. However, on the contrary, this method provides an adverse effect to the thermal permanent breakdown of the holes, which is generated in the avalanche breakdown. In other words, with respect to the p-type layer provided for the increase in the high tolerance voltage of the power-FET, excessive holes can be discharged to the source or the ground. Thus, in the case where a negative bias is applied to the gate, a barrier is provided which prevents the outflow of the holes to the gate.
FIG. 1 is a general model view showing a cross section of a power-FET having a structure free from the usage of a p-type layer buffer. In FIG. 1, a non-doped layer 7 is laminated on the semi-insulation substrate 8 and a channel n-type layer 6 is formed. Then, a source electrode 1 is provided via a high concentration n-type layer 4 of the source, and a drain electrode 3 is provided via a high concentration n-type layer 5 of the drain. Between the source electrode 1 and the drain electrode 3, a gate electrode 2 is provided. Between the gate electrode 2 and the drain electrode 3, a drift region 9 is provided. Incidentally, an explanation is made on the n-channel FET as an example here, but completely the same operation is carried out with the p-channel FET by inverting the p and n codes.
The structure shown in FIG. 1 is such that a substrate having a predetermined epitaxial structure is prepared, and an element is separated and prepared by selectively providing the channel n-type layer with the semi- insulation by means of the ion implantation of boron and oxygen. Symbol X in FIG. 1 denotes an ion implantation region. This structure is widely used in the GaAs power-FET, and the tolerance voltage is not improved unlike the MOSFET even when a distance between the gate and the drain is increased.
FIG. 2 is a view showing a structure in which an embedded p-type layer 10 is added to the structure shown in FIG. 1. In FIG. 2, like parts in FIG. 1 is denoted by like reference numerals. The embedded p-type layer 10 in FIG. 2 is surrounded by the semi-insulation substrate 8 and a non-doped layer 7 with the result that the embedded p-type layer 10 is electrically drifting. This structure has a problem that the potential of the embedded p-type layer 10 is negatively biased with the negative bias of the gate and the charged pumping phenomenon, and the drain current is lowered so that the power cannot be generated. This structure also has a disadvantage that the holes resulting from the avalanche breakdown invites an increase in the drain current, which tends to lead to a permanent breakdown.
FIG. 3 is a potential view in the direction of the cross section of the channel in the case where an excessively large negative bias is applied to the gate of the transistor of FIG. 2. At the same time, there is also shown a case in which the gate is set to the ON state.
In FIG. 3, reference numeral 15 denotes a conducted band in the case where the gate voltage is not applied thereto. Reference numeral 16 denotes a charged band in the case where the gate voltage is not applied thereto. Furthermore, reference numeral 17 denotes a conducted band in the case where a large negative bias is applied to the gate voltage. Reference numeral 18 denotes a charged band in the case where a large negative voltage is applied to the gate voltage. Incidentally, reference numeral 19 denotes channel electrons, and reference numeral 20 denotes holes.
In the case where a normal bias is applied to the gate, and the channel is set to the ON state, a zero bias or an opposite bias of the p-n junction is applied between the channel n region, and the buffer layer or the p-type layer of the substrate with the result that the electrons and holes are being separated. Consequently, the holes will not flow out to the gate electrode 2, the source electrode 1 and the drain electrode 3.
However, when the negative bias is applied to the gate, the electrons flow into the source electrode 1 or the drain electrode 3 with the result that the electron current is set to the OFF state and is stabilized. The holes are attracted to the direction of the gate electrode 2. When the gate bias is low, a barrier against the holes at the end of the p-type layer exists. However, the barrier soon disappears with a small gate bias. Then, as denoted by an arrow 21, the holes 20 begin to flow into the gate electrode 2. In the case of the MOSFET, there is a disadvantage in that the gate oxide film constitutes a barrier and the holes will not flow into the gate electrode 2, but the holes are accumulated in the interface thereby generating a cause of a parasitic capacity.
An object of the present invention is to provide a field effect transistor and a method for manufacturing the field effect transistor, the transistor being capable of improving the tolerance voltage of a drain either in the ON state or in the OFF state or in both states and realizing a high output FET by providing a buffer layer structure which constitutes a barrier with respect to the outflow of the holes at the time of the application of the negative bias of the gate in the power-FET in which the p-type layer is introduced into a portion underneath the channel, wherein the holes which are generated in the avalanche breakdown flow smoothly into the p-type layer and are discharged into the source or into the ground.
The field effect transistor according to the present invention includes a first conductive type channel layer, a second conductive type substrate, a first conductive type depletion semiconductor layer which is provided between the substrate and the channel layer, and a first conductive layer and a second conductive layer which are provided between the depletion semiconductor layer and the substrate to form a potential barrier. Then, the field effect transistor is characterized in that the potential barrier formed of the first conductive layer and the second conductive layer serves as a barrier for preventing the second conductive type carrier from flowing from the substrate in the direction of the gate electrode even in the case where an excessively large voltage is applied to the gate electrode which voltage is larger than the bias required for cutting off the channel of the channel layer described above.
Furthermore, a low concentration second conductive layer having a lower concentration than the second conductive layer and the substrate is provided between the second conductive layer provided between the depletion semiconductor layer and the substrate, and the substrate.
A method for manufacturing the field effect transistor according to the present invention is a method for manufacturing a field effect transistor having a first conductive type channel layer, the method comprising the steps of:
forming a second conductive layer on a second conductive type substrate;
forming a first conductive type layer on the second conductive type layer;
forming a non-doped layer on a first conductive type layer; and
forming a channel layer on the non-doped layer;
wherein the first conductive type layer is depleted and a barrier against the second conductive type carrier is formed with the first conductive type layer and the second conductive type layer.
In the present invention, in order to attain the object described above, a structure is used in which a p-type layer, an n-type layer, a non-doped layer and a channel layer are laminated in order on the p-type substrate, the n-type layer is depleted, and at the same time, an impurity concentration and a thickness of each of the layers are set in such a manner that the barrier against the holes formed of the p-type layer and the n-type layer serves as a barrier even in the case where an excessively large negative voltage is applied to the gate. Furthermore, the structure is constituted in such a manner that a low concentration p-type layer is provided between the p-type layer and the p-type substrate, and the holes of the upper part p-type layer are depleted at a drain voltage on a certain degree. Otherwise, a p-type layer having a high concentration of 1xc3x971019 cmxe2x88x923 is provided on the p-type substrate. Otherwise, a semi-insulation or an insulation substrate are used in the place of the p-type substrate, and a high concentration p-type layer is provided thereon. In such a case, either a high concentration p-type layer is exposed to the surface and an electrode is provided, or a via hole is provided for connecting the source electrode and the rear surface of the substrate so that the via hole metal and a high concentration p-type layer directly come into contact with each other.
The barrier on which the p-type layer and the n-type layer are located adjacent to each other forms a potential distribution on the step and becomes a barrier having directivity respectively with respect to the electrons and the holes. Thus, the barrier provides a structure in which holes do not flow out from the p-type layer, but the inflow of the holes can not be prevented. Furthermore, the change in the potential of the p-type layer is prevented, and either the p-type substrate is used for discharging the holes, or an electrode is provided on the p-type layer with the result the potential is fixed. When a high concentration p-type layer having a concentration of 1xc3x971019 cmxe2x88x923 or more is used on a part of the p-type layer, an ohmic contact can be obtained with a tunnel effect only with the contact with the shot key metal. With these structures, the potential of the p-type layer is fixed, and, at the same time, the gate leak can be eliminated. Consequently, both in the OFF state and in the ON state, a device having a high-tolerance voltage can be realized.